In some conventional integrated circuit devices, to control the current through output pads, a plurality of open drain output buffers, which are connected to the output pads, are turned on or off. Typically, the plurality of open drain output buffers is controlled by a digital signal that comprises multiple bits. For example, each open drain output buffer may be associated with a bit of a digital signal and is turned on or off in response to the logic level of the digital signal bit. A termination resistance is controlled in a similar way to control the current through the output pads.
The current through the output pads and/or the termination resistance is an analog quantity that is controlled by a digital value. The current and/or the termination resistance changes by a specific amount whenever the corresponding digital value changes by 1 bit. The change of an analog value with respect to the minimum change of a digital value may be referred to as the resolution of the minimum change in the digital value. Because the resolution is limited, it may be difficult to accurately control an analog value of interest.
FIGS. 1A and 1B illustrate an analog value that is generated in response to a digital signal. FIGS. 1A and 1B illustrate potential errors that may occur when an analog value is controlled using a digital signal. For example, one error that can occur when the current through the output pads is controlled by the size of the open drain output buffer will be described with reference to FIGS. 1A and 1B.
Typically, the size of the open drain output buffer is determined by using a digital signal to control the open drain output buffers while determining if the current through the output pads reaches a reference current. Referring now to FIG. 1A, while an evaluation signal EVALS is driven to a logic high level, it is determined if the current through output pads (not shown) reaches a reference current value REFV while changing a digital signal. MIN_RES represents the minimum change in the current through the output pads when the least significant bit of the digital signal changes.
When the current through the output pads reaches the reference current value REFV, the evaluation signal EVALS is driven to a logic low level and respective bits of the digital signal are maintained at the logic levels they have when the evaluation signal EVALS is driven to the logic low level. As shown in FIG. 1A, the current through the output pads has an error ERR1 with respect to the reference current value REFV.
The error ERR1 may be equal to or less than the change in the current through the output pads with respect to the least significant bit change in a digital signal. In a typical Rambus DRAM, the reference current value REFV is approximately 30 mA, and the digital signal that controls open drain output buffers comprises 7 bits.
When the digital signal comprises 7 bits, the current through the output pads can be classified into 128 (27) levels. A device including the output pads may be designed such that the current through the output pads is more than the reference current value REFV so that the proper maximum current can be obtained even when the environment changes. In other words, the current through the output pads may be approximately 20% more than the reference current value REFV. Thus, for a typical Rambus DRAM, a maximum current of approximately 36 mA may flow through the output pads. The open drain output buffer may control a current through the output pads that ranges from about 36 mA to 70 mA according to the PVT (Process, Voltage, Temperature) conditions. As a result, the resolution of the least significant bit change in the digital signal is between about 0.3 mA and 0.6 mA.
It is generally desirable for the error range of the current through the output pads to be about −1.5 mA-+1.5 mA based on typical Rambus DRAM specifications. In other words, the difference between the current through the output pads and the reference current should fall into this range regardless of various manufacturing conditions, such as high or low temperature, a high or low supply voltage Vdd, and the like. Thus, it may be desirable for the resolution of a change in the least significant bit of the digital signal to be less than the range of about 0.3 mA-0.6 mA.
Referring now to FIG. 1B an error ERR2 between the current through the output pads and the reference current value REFV is relatively small. In other words, the difference between the current through the output pads and the reference current value REFV may be equal to the maximum value of the resolution of the least significant bit of the digital signal as shown in FIG. 1A or less than the minimum value of the resolution of the least significant bit of the digital signal as shown in FIG. 1B. Thus, the error with respect to a final target value can be reduced by decreasing the change in the current through the output pads with respect to a change in the least significant bit of the digital signal, i.e., the resolution of the least significant bit of the digital signal.
FIG. 2 illustrates a conventional digital control system for generating an analog value. Referring to FIG. 2, a comparing unit 240 compares an analog value ANALV, which is generated by an analog control unit 230, with a reference value REFV and generates a control signal CTRL based on the result of the comparison. The analog value ANALV may correspond to the current through the output pads and the reference value REFV may correspond to the reference current. If the analog value ANALV, i.e., the current through the output pads, is less than the reference value REFV, then the control signal CTRL is generated at a first level. If the analog value ANALV is greater than the reference value REFV, then the control signal CTRL is generated at a second level.
A counter 210 counts the number of pulses of a clock signal CLK in response to an evaluation signal EVALS. When the control signal CTRL is at the first level, the counter 210 increases the number of pulses of a clock signal CLK that it counts. When the control signal CTRL is at the second level, the counter 210 decreases the number of pulses of the clock signal CLK that it counts. In other words, as the analog value ANALV approaches the reference value REFV, the control signal CTRL is alternately generated at the first and second levels. As a result, the number of pulses of the clock signal CLK counted by the counter 210 alternately increases and decreases.
During repetition of counting up and down, the counter 210 outputs the number of pulses of the clock signal CLK as a count value SA when the evaluation signal EVALS is deactivated. The count value SA is stored in a register 220. The count value SA stored in the register 220 is output to the analog control unit 230. The analog control unit 230 generates the analog value ANALV, i.e., the current through output pads, in response to the count value SA. The current through the output pads has an error ERR1 or ERR2 with respect to a reference current value REFV associated therewith as shown in FIGS. 1A and 1B.